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HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS90C320
User's Manual (Ver. 1.2)
REVISION HISTORY
VERSION 1.2 (Oct. 2000) This book Correct the pin number of 44-MQFP package type on page 6.
VERSION 1.1 (Oct. 1999) Before version
Version 1.2 Published by MCU Application Team Copy right (c)2001 Hynix semiconductor, All right reserved.
Additional information of this manual may be served by Hynix semiconductor offices in Korea or Distributors and Representatives listed at address directory. Hynix semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
GMS90C320
Device Naming Structure
H(G)MS90X320 XXXX
Frequency Blank: 24MHz 40: 40MHz 50: 50MHz Hynix semiconductor MCU MCU Series Package Type Blank: 40PDIP PL: 44PLCC Q: 44MQFP Enhanced ROM-less version Operating Voltage C: Normal voltage L: Low voltage
OCT. 2000 Ver 1.2
GMS90C320
GMS90C320 ordering information
Operating Voltage (V) Device Name GMS90C320 40 GMS90C320 PL40 GMS90C320 Q40 4.25~5.5 GMS90C320 50 GMS90C320 PL50 GMS90C320 Q50 2.7~5.5 GMS90L320 GMS90L320 PL GMS90L320 Q ROM-less 256 50 40PDIP 44PLCC 44MQFP 40PDIP 44PLCC 44MQFP ROM size (bytes) ROM-less RAM size (bytes) 256 Operating max. Frequency (MHz) 40 Package Type 40PDIP 44PLCC 44MQFP
ROM-less
256
24
OCT. 2000 Ver 1.2
GMS90C320
GMS90C320/L320
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER ROM-less Version for 90C52
Operating Voltage (V) 4.25~5.5 2.7~5.5
Device Name GMS90C320 GMS90L320
ROM ROM-less ROM-less
RAM 256 x 8bit 256 x 8bit
Operating Frequency (MHz) 40/50 24
Features
* Fully compatible to standard MCS-51 microcontroller * Versions for 40/50 MHz operating frequency * Low voltage version for 24MHz operating frequency * 256 bytes of on-chip data RAM * 64K external program memory space * 64K external data memory space * Four 8-bit ports * Three 16-bit Timers/Counters (Timer 2 with up/down counter feature) * USART * Six interrupt sources, two priority levels * Power saving Idle and power down mode * 2.7Volt low voltage version available * P-DIP-40, P-LCC-44, P-MQFP-44 package
RAM 256 x 8 T0 T2 T1 ROM-less CPU 8-BIT USART
PORT0 PORT1
I/O I/O
PORT2 PORT3
I/O I/O
The GMS90C320 described in this document is compatible with the standard 80C32 can be used for all present standard 80C32 applications.
OCT. 2000 Ver 1.2
1
GMS90C320
44-PLCC Pin Configuration
(top view)
(P-LCC-44)
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2 41
P1.3
44
43
42
40
6
5
4
3
2
1
P0.3/AD3
P1.0/T2
P1.4
P1.2
N.C.
VCC
P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
39 38 37 36 35 34 33 32 31 30 29
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA N.C. ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
P2.2/A10
P2.3/A11
2
P2.4/A12
XTAL2
WR/P3.6
RD/P3.7
XTAL1
P2.0/A8
P2.1/A9
VS S
N.C.
OCT. 2000 Ver 1.2
GMS90C320
40-PDIP Pin Configuration
(top view)
(P-DIP-40)
T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VS S
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
OCT. 2000 Ver 1.2
3
GMS90C320
44-PLCC Pin Configuration
(top view)
(P-MQFP-44)
P1.1/T2EX
P0.0/AD0
P0.1/AD1
P0.2/AD2 35
P1.3
38
37
36
44
43
42
41
40
39
34
P0.3/AD3
P1.0/T2
P1.4
P1.2
N.C.
VCC
P1.5 P1.6 P1.7 RESET RxD/P3.0 N.C. TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5
1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 11
33 32 31 30 29 28 27 26 25 24 22 23
P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA N.C. ALE PSEN P2.7/A15 P2.6/A14 P2.5/A13
WR/P3.6
RD/P3.7
XTAL2
XTAL1
N.C.
P2.0/A8
P2.1/A9
P2.2/A10
P2.3/A11
4
P2.4/A12
VSS
OCT. 2000 Ver 1.2
GMS90C320
VC C
VS S
XTAL1 XTAL2
Port 0 8-bit Digital I/O Port 1 8-bit Digital I/O Port 2 8-bit Digital I/O
RESET
EA ALE PSEN Port 3 8-bit Digital I/O
Logic Symbol
OCT. 2000 Ver 1.2
5
GMS90C320
Pin Definitions and functions
Pin Number Symbol
P-LCC-44 P-DIP-40 P-MQFP44
Input/ Output I/O
Function Port1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the pulls-ups (IIL , in the DC characteristics). Pins P1.0 and P1.1 also. Port 1 also receives the low-order address byte during program memory verification. Port1 also serves alternate functions of Timer 2. P1.0/T2: Timer/counter 2 external count input P1.1/T2EX: Timer/counter 2 trigger input
P1.0-P1.7
2-9
1-8
40-44, 1-3
2 3 P3.0-P3.7 11,1319
1 2 10-17
40 41 5, 713 I/O
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs, port 3 pins being externally pulled low will source current (IIL , in the DC characteristics) because of internal pulls-up resistors. Port 3 also serves the special features of the 80C51 family, as listed below. P3.0/RxD P3.1 / TxD P3.2 / INT0 P3.3 / INT1 P3.4 / T0 P3.5 / T1 P3.6 / WR P3.7 / RD receiver data input (asynchronous) or data input output (synchronous) of the serial interface 0 transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 interrupt 0 input / timer 0 gate control interrupt 1 input / timer 1 gate control counter 0 input counter 1 input the write control signal latches the data byte from port 0 into the external data memory the read control signal enables the external data memory to port 0
11 13 14 15 16 17 18 19 XTAL2 XTAL1 20 21
10 11 12 13 14 15 16 17 18 19
5 7 8 9 10 11 12 13 14 15 O I
XTAL2 Output of the inverting oscillator amplifier XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divideby-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed.
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OCT. 2000 Ver 1.2
GMS90C320
Pin Number Symbol
P-LCC-44 P-DIP-40 P-MQFP44
Input/ Output I/O
Function Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 2 pins that are externally pulled low will source current because of the pulls-ups (IIL , in the DC characteristics). Port 2 emits the highorder address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 special function register. The Program Store Enable The read strobe to external program memory when the device is executing code from the external program memory. PSEN is activated twice each machine cycle, except that two PSEN activation are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VS S permits power-on reset using only an external capacitor to VC C . The Address Latch Enable Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. External Access Enable EA must be external held low to enable the device to fetch code from external program memory locations 0000H to FFFFH . If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than its internal memory size. Port 0 Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the GMS97C5x. External pull-up resistors are required during program verification. Circuit ground potential Supply terminal for all operating modes No connection
P2.0-P2.7
24-31
21-28
18-25
PSEN
32
29
26
O
RESET
10
9
4
I
ALE
33
30
27
O
EA
35
31
29
I
P0.0-P0.7
43-36
39-32
37-30
I/O
VS S VC C N.C.
22 44 1,12, 23,34
20 40 -
16 38 6,17, 28,39
-
OCT. 2000 Ver 1.2
7
GMS90C320
Function Description
The GMS90 series is fully compatible to the standard 8051 microcontroller family. It is compatible with the standard 80C32. While maintaining all architectural and operational characteristics of the standard 80C32, the GMS90C320 incorporates some enhancements in the Timer 2 unit. Figure 1 shows a block diagram of the GMS90C320
XTAL1 XTAL2
OSC & Timing
RAM 256 x 8
RESET
CPU
Timer 0 ALE PSEN EA Timer 1
Port 0
Port 0 8-bit Digital I/O Port 1 8-bit Digital I/O Port 2 8-bit Digital I/O Port 3 8-bit Digital I/O
Port 1 Timer 2 Port 2 Interrupt Unit Port 3 Serial Channel
Figure 1 Block Diagram of the GMS90C320
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OCT. 2000 Ver 1.2
GMS90C320
CPU
The GMS90C320 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0s.
Special Function Register PSW
MSB Bit No. Addr. D0H 7 CY 6 AC 5 F0 4 RS1 3 RS2 2 OV 1 F1
LSB 0 P PSW
Bit CY AC F0 RS1 0 0 1 1 OV F1 P RS0 0 1 0 1
Function Carry Flag Auxiliary Carry Flag (for BCD operation) General Purpose Flag Register Bank select control bits Bank 0 selected, data address 00 H -07H Bank 1 selected, data address 08 H -0FH Bank 2 selected, data address 10 H -17H Bank 3 selected, data address 18 H -1FH Overflow Flag General Purpose Flag Parity Flag Set/cleared by hardware each instruction cycle to indicate an odd/ even number of "one" bits in the accumulator, i.e. even parity.
Reset value of PSW is 00H .
OCT. 2000 Ver 1.2
9
GMS90C320
Special Function Registers
All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 27 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in Table 1, Table 2, and Table 3. In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the functional blocks of the GMS90C320. Table 3 illustrates the contents of the SFRs.
Table 1 Special Function Registers in Numeric Order of their Addresses Contents after Reset FFH 07H 00H 00H XXH 2) XXH 2) XXH 2) 0XXX0000B 2) 00H 00H 00H 00H 00H 00H XXH 2) XXH 2) FFH 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) Contents after Reset FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 0X000000B 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XX000000B 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2)
Address 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8CH 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH
1) 2)
Register P01) SP DPL DPH reserved reserved reserved PCON TCON1) TMOD TL0 TL1 TH0 TH1 reserved reserved P11) reserved reserved reserved reserved reserved reserved reserved SCON1) SBUF reserved reserved reserved reserved reserved reserved
Address A0H A1H A2H A3H A4H A5H A6H A7H A8H A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH
Register P21) reserved reserved reserved reserved reserved reserved reserved IE1) reserved reserved reserved reserved reserved reserved reserved P31) reserved reserved reserved reserved reserved reserved reserved IP1) reserved reserved reserved reserved reserved reserved reserved
: Bit-addressable Special Function Register : X means that the value is indeterminate and the location is reserved
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OCT. 2000 Ver 1.2
GMS90C320
Table 1 Special Function Registers in numeric order of their addresses (cont'd) Contents after Reset XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 00H XXXXXXX0B 2) 00H 00H 00H 00H XXH 2) XXH 2) 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) Contents after Reset 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2)
Address C0H C1H C2H C3H C4H C5H C6H C7H C8H C9H CAH CBH CCH CDH CEH CFH D0H D1H D2H D3H D4H D5H D6H D7H D8H D9H DAH DBH DCH DDH DEH DFH
1) 2)
Register reserved reserved reserved reserved reserved reserved reserved reserved T2CON1) T2MOD RC2L RC2H TL2 TH2 reserved reserved PSW1) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
Address E0H E1H E2H E3H E4H E5H E6H E7H E8H E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH
Register ACC1) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved B1) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
: Bit-addressable Special Function Register : X means that the value is indeterminate and the location is reserved
OCT. 2000 Ver 1.2
11
GMS90C320
Table 2 Special Function Registers - Functional Blocks Content after Reset 00H 00H 00H 00H 00H 07H 0X000000B 2) XX000000B 2) FFH FFH FFH FFH 0XXX0000B 2) XXH 3) 00H 00H 00H 00H 00H 00H 00H 00H XXXXXXX0B 2) 00H 00H 00H 00H 0XXX0000B 2)
Block CPU
Symbol ACC B DPH DPL PSW SP IE IP P0 P1 P2 P3 PCON SBUF SCON TCON TH0 TH1 TL0 TL1 TMOD T2CON T2MOD RC2H RC2L TH2 TL2 PCON
Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Interrupt Enable Register Interrupt Priority Register Port 0 Port 1 Port 2 Port 3 Power Control Register Serial Channel Buffer Register Serial Channel 0 Control Register Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload Capture Register, High Byte Timer 2 Reload Capture Register, Low Byte Timer 2, High Byte Timer 2, Low Byte Power Control Register
Address E0H 1) F0H 1) 83H 82H D0H 1) 81H A8H 1) B8H 1) 80H 1) 90H 1) A0H 1) B0H 1) 87H 99H 98H 1) 88H 1) 8CH 8DH 8AH 8BH 89H C8H 1) C9H CBH CAH CDH CCH 87H
Interrupt System Ports
Serial Channels
Timer 0 / Timer 1
Timer 2
Power Saving Modes
1) 2) 3)
Bit-addressable Special Function Registers This special function register is listed repeatedly since some bits of it also belong to other functional blocks X means that the value is indeterminate and the location is reserved
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OCT. 2000 Ver 1.2
GMS90C320
Table 3 Contents of SFRs, SFRs in Numeric Order Address 80H 81H 82H 83H 87H 88H 89H 8AH 8BH 8CH 8DH 90H 98H 99H A0H A8H B0H B8H C8H C9H Register P0 SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 P1 SCON SBUF P2 IE P3 IP T2CON T2MOD TF2 EXF2 PT2 RCLK PS TCLK PT1 EXEN2 PX1 TR2 PT0 C/T2 PX0 CP/RL2 DCEN EA ET2 ES ET1 EX1 ET0 EX0 SM0 SM1 SM2 REN TB8 RB8 TI RI SMOD TF1 GATE TR1 C/T TF0 M1 TR0 M0 GF1 IE1 GATE GF0 IT1 C/T PDE IE0 M1 IDLE IT0 M0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR bit and byte addressable SFR not bit addressable This bit location is reserved.
OCT. 2000 Ver 1.2
13
GMS90C320
Table 3 Contents of SFRs, SFRs in Numeric Order (cont'd) Address CAH CBH CCH CDH D0H E0H F0H Register RC2L RC2H TL2 TH2 PSW ACC B CY AC F0 RS1 RS0 OV F1 P
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SFR bit and byte addressable SFR not bit addressable This bit location is reserved.
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OCT. 2000 Ver 1.2
GMS90C320
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
Table 4 Timer/Counter 0 and 1 Operating Modes TMOD Mode 0 Description GATE 8-bit timer/counter with a divide-by-32 prescaler 16-bit timer/counter 8-bit timer/counter with 8-bit autoreload Timer/counter 0 used as one 8-bit timer/counter and one 8bit timer Timer 1 stops X C/T X M1 0 M0 0 Internal
OSC -----------------12 x 32 OSC --------------12 OSC --------------12
Input Clock External (Max.)
OSC -----------------24 x 32 OSC --------------24 OSC --------------24

1 2 3
X X
X X
0 1
1 0
X
X
1
1
OSC --------------12
OSC --------------24
In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is OSC 12 . In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is OSC 24 . External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 2 illustrates the input clock logic.
fO SC
/12
OSC
C/T TMOD 0
12
P3.4/T0 P3.5/T1 max. fO SC /24 TR 0/1 TCON GATE TMOD P3.2/INT0 P3.3/INT1
Timer 0/1 Input Clock 1 Control
Figure 2 Timer/Counter 0 and 1 Input Clock Logic
OCT. 2000 Ver 1.2
15
GMS90C320
Timer 2
Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5.
Table 5 Timer/Counter 2 Operating Modes
T2CON
Input Clock
TR2 T2MO D DECN T2CON EXEN P1.1 T2EX
Mode
RxCLK or TxCLK
CP/ RL2
Remarks Internal reload upon overflow reload trigger (falling edge) Down counting Up counting 16-bit Timer/Counter (only up-counting) capture TH1, TL2 RC2H, RC2L no overflow interrupt request (TF2) extra external interrupt ("Timer 2") Timer 2 stops
External (P1.0/T2)
16-bit Autoreload
0 0 0 0 0 0
0 0 0 0 1 1 X X X
1 1 1 1 1 1 1 1 0
0 0 1 1 X X X X X
0 1 X X 0 1 0 1 X
X 0 1 X X X
OSC --------------12
OSC max. ---------------
24
16-bit Capture
OSC --------------12
OSC max. ---------------
24
Baud Rate Generator
1 1
OSC --------------12
OSC max. ---------------
24
off
X
-
-
1Note: =
falling edge
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OCT. 2000 Ver 1.2
GMS90C320
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 7.
Table 6 USART Operating Modes SCON Mode SM0 0 0 SM1 0
OSC --------------12
Baudrate
Description Serial data enters and exits through RxD. TxD outputs the shift clock. 8-bit are transmitted/received (LSB first) 8-bit UART 10 bits are transmitted (through TxD) or received (RxD) 9-bit UART 11 bits are transmitted (through TxD) or received (RxD) 9-bit UART Like mode 2 except the variable baud rate
1
0
1
Timer 1/2 overflow rate
2
1
0
OSC OSC --------------- or --------------32 64
3
1
1
Timer 1/2 overflow rate
Table 7 Formulas for Calculating Baud rates Baud Rate derived from Oscillator
Interface Mode 0 2
Baud rate
OSC --------------12
2 SMOD x OSC -----------------------------------------64 e 2 SMOD x timer 1 overflow rat -------------------------------------------------------------------------------32 2 SMOD x OSC ---------------------------------------------------------32 x 12 x ( 256 - TH1 )
OSC -----------------------------------------------------------------------------32 x [ 65536 - ( RC2H,RC2L ) ]
Timer 1 (16-bit timer) (8-bit timer with 8-bit autoreload)
1, 3
1, 3
Timer 2
1, 3
OCT. 2000 Ver 1.2
17
GMS90C320
Interrupt System
The GMS90C320 provides 6 interrupt sources with two priority levels. Figure 3 gives a general overview of the interrupt sources and illustrates the request and control flags.
High Priority Low Priority Timer 0 Overflow TF0 TCON.5 ET0 IE.1 PT0 IP.1
Timer 1 Overflow
TF1 TCON.7 ET1 IE.3 PT1 IP.3
Timer 2 Overflow
TF2 T2CON.7 EXF2 T2CON.6
P1.1/ T2EX EXEN2 T2CON.3 USART
ET2 IE.5
PT2 IP.5
RI SCON.0 TI SCON.1
ES IE.4
PS IP.4
P3.2/ INT0 IT0 TCON.0
IE0 TCON.1 EX0 IE.0 PX0 IP.0
P3.3/ INT1 IT1 TCON.2
IE1 TCON.3 EX1 IE.2 EA IE.7 PX1 IP.2
Figure 3 Interrupt Request Sources
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OCT. 2000 Ver 1.2
GMS90C320
Table 8 Interrupt Sources and their Corresponding Interrupt Vectors Source (Request Flags) IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 Vector External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt Vector Address 0003H 000BH 0013H 001BH 0023H 002BH
A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A highpriority interrupt cannot be interrupted by any other interrupt source.
If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9.
Table 9 Interrupt Priority-Within-Level Interrupt Source IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt Priority High
Low
OCT. 2000 Ver 1.2
19
GMS90C320
Power Saving Modes
Two power down modes are available, the Idle Mode and Power Down Mode. The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview of the power saving modes.
Table 10 Power Saving Modes Overview Mode Idle mode Entering Instruction Example ORL PCON,#01H Leaving by - enabled interrupt - Hardware Reset Remarks CPU is gated off CPU status registers maintain their data. Peripherals are active Oscillator is stopped, contents of on-chip RAM and SFR's are maintained (leaving Power Down Mode means redefinition of SFR contents).
Power-Down Mode
ORL PCON,#02H
Hardware Reset
In the Power Down mode of operation, VC C can be reduced to minimize power consumption. It must be ensured, however, that VC C is not reduced before the Power Down mode is invoked, and that VC C is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down Mode also restarts the oscillator. The reset should not be activated before VC C is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset).
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OCT. 2000 Ver 1.2
GMS90C320
Absolute Maximum Ratings
Ambient temperature under bias (TA ) .......................................................................................................-40 to + 85C Storage temperature (TS T )..........................................................................................................................-65 to + 150C Voltage on VC C pins with respect to ground (VS S ).....................................................................................-0.5 V to 6.5 V Voltage on any pin with respect to ground (VSS ).......................................................................................-0.5 to VC C + 0.5 V Input current on any pin during overload condition ..................................................................................-10 mA to + 10 mA Absolute sum of all input currents during overload condition ..................................................................| 100 mA | Power dissipation.......................................................................................................................................TBD
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VC C or VIN < VS S ) the Voltage on VC C pins with respect to ground (VS S ) must not exceed the values defined by the absolute maximum ratings.
OCT. 2000 Ver 1.2
21
GMS90C320
DC Characteristics
DC Characteristics for GMS90C320
VC C = 5V + 10%, -15%; VS S =0V; TA = 0C to 70C
Parameter Input low voltage (except EA, RESET) Input low voltage (EA) Input low voltage (RESET) Input high voltage (except XTAL1, EA, RESET) Input high voltage to XTAL1 Input high voltage to EA, RESET Output low voltage (ports 1, 2, 3) Output low voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 12MHz3) Idle mode, 12MHz3) Active mode, 24 MHz3) Idle mode, 24MHz3) Active mode, 40 MHz3) Idle mode, 40 MHz3) Active mode, 50 MHz3) Idle mode, 50 MHz3) Power Down Mode3) Symbol VIL VIL1 VIL2 VIH VIH 1 VIH 2 Limit Values Min. -0.5 -0.5 -0.5 0.2VC C + 0.9 0.7VC C 0.6VC C Max. 0.2VC C - 0.1 0.2VC C - 0.3 0.2VC C + 0.1 VC C + 0.5 VC C + 0.5 VC C + 0.5 0.3 0.45 1.0 0.3 0.45 1.0 Unit V V V V V V Test Conditions IO L = 100A IO L = 1.6mA1) IO L = 3.5mA IO L = 200A IO L = 3.2mA1) IO L = 7.0mA IO H = -80A IO H = -10A IO H = -800A2) IO H = -80A2) VIN = 0.45V VIN = 2.0V 0.45 < VIN < VC C fC =1MHz, TA = 25C VC C = 5V4) VC C = 5V5) VC C = 5V4) VC C = 5V5) VC C = 5V4) VC C = 5V5) VC C = 5V4) VC C = 5V5) VC C = 5.5V6)
VO L
-
V
VO L1
2.4 0.9VC C 2.4 0.9VC C -10 -65 -
V
VO H
V
VO H 1 IIL IT L ILI CIO IC C IC C IC C IC C IC C IC C IC C IC C IP D
-
V A A A pF mA mA mA mA mA mA mA mA A
-50 -650 1 10 16 7.5 26 13.5 44 18 55 22.5 50
22
OCT. 2000 Ver 1.2
GMS90C320
1)
Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VO L of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitttrigger strobe input. Capacitive loading on ports 0 and 2 may cause the VO H on ALE and PSEN to momentarily fall below the 0.9VC C specification when the address lines are stabilizing. ICC m ax at other frequencies is given by: active mode: IC C = 1.0 x O SC + 3.16 idle mode: IC C = 0.37 x O SC + 3.63 where O SC is the oscillator frequency in MHz. ICC values are given in mA and measured at VC C = 5V. ICC (active mode) is measured with: XTAL1 driven with tCLC H , tC HCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.; EA = Port 0 = RESET = VCC ; all other pins are disconnected. I C C would be slightly higher if a crystal oscillator is used (appr. 1mA). ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLC H , tC HCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.; RESET = EA = VSS ; Port0 = VCC ; all other pins are disconnected; IPD (Power Down Mode) is measured under following conditions: EA = Port 0 = VCC ; RESET = VSS ; XTAL2 = N.C.; XTAL1 = VS S ; all other pins are disconnected.
2)
3)
4)
5)
6)
OCT. 2000 Ver 1.2
23
GMS90C320
DC Characteristics for GMS90L320
VC C = 3.3V + 0.3V, -0.6V; VS S =0V; TA = 0C to 70C
Limit Values Parameter Input low voltage Input high voltage Output low voltage (ports 1, 2, 3) Output low voltage (port 0, ALE, PSEN) Output high voltage (ports 1, 2, 3) Output high voltage (port 0 in external bus mode, ALE, PSEN) Logic 0 input current (ports 1, 2, 3) Logical 1-to-0 transition current (ports 1, 2, 3) Input leakage current (port 0, EA) Pin capacitance Power supply current: Active mode, 16 MHz3) Idle mode, 16MHz3) Active mode, 24MHz3) Idle mode, 24MHz3) Power Down Mode3) Symbol Min. VIL VIH VO L VO L1 VO H -0.5 2.0 2.0 0.9VC C 2.0 0.9VC C -1 -25 Max. 0.8 VC C + 0.5 0.45 0.30 0.45 0.30 V V V V V IO L = 1.6mA1) IO L = 100A1) IO L = 3.2mA1) IO L = 200A1) IO H = -20A IO H = -10A IO H = -800A2) IO H = -80A2) VIN = 0.45V VIN = 2.0V 0.45 < VIN < VC C fC = 1MHz TA = 25C VC C = 3.3V4) VC C = 3.3V5) VC C = 3.3V4) VC C = 3.3V5) VC C = 3.6V6) Unit Test Conditions
VO H 1
-
V A A A pF
IIL IT L ILI CIO
-50 -250 1 10
IC C IC C IC C IC C IP D
-
10 5.25 16 8.25 10
mA mA A
24
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics
Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a `t' (stand for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for.
A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, tA VLL = Time from Address Valid to ALE Low tLLPL = Time from ALE Low to PSEN Low
OCT. 2000 Ver 1.2
25
GMS90C320
AC Characteristics for 12MHz version
VCC = 5V: VCC = 3.3V: Variable clock: VC C = 5V + 10%, -15%; VS S = 0V; TA = 0C to 70C (CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF) VC C = 3.3V + 0.3V, -0.6V; VS S = 0V; TA = 0C to 70C (CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF) Vcc = 5V: 1/tC LC L = 3.5 MHz to 12 MHz Vcc = 3.3V: 1/tC LC L = 1 MHz to 12 MHz
External Program Memory Characteristics
12 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN
1)
Variable Oscillator 1/tCLC L = 3.5 to 12MHz Min. 2tC LC L -40 tC LC L -40 tC LC L -40 tC LC L -25 3tC LC L -35 0 tC LC L -8 -10 Max. 4tC LC L -100 3tC LC L -100 tC LC L -20 5tC LC L -115 -
Unit
Max. 233 150 63 302 -
tLH LL tA VLL tLLA X tLLIV tLLP L tP LP H tP LIV tP XIX tP XIZ 1) tP XA V 1) tA VIV tA ZP L
127 43 43 58 215 0 75 -10
ns ns ns ns ns ns ns ns ns ns ns ns
Interfacing the GMS90C320 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers.
26
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 12MHz version External Data Memory Characteristics
12 MHz Oscillator Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tR LR H tW LW H tLLA X 2 tR LD V tR H D X tR H D Z tLLD V tA VD V tLLW L tA VW L tW H LH tQ VW X tQ VW H tW H Q X tR LA Z 400 400 127 0 200 203 43 33 433 33 Max. 252 97 517 585 300 123 0 Variable Oscillator 1/tC LCL = 3.5 to 12MHz Min. 6tC LC L -100 6tC LC L -100 2tC LC L -40 0 3tC LC L -50 4tC LC L -130 tC LC L -40 tC LC L -50 7tC LC L -150 tC LC L -50 Max. 5tC LC L -165 2tC LC L -70 8tC LC L -150 9tC LC L -165 3tC LC L +50 tC LC L +40 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (12MHz) External Clock Drive
Parameter Oscillator period (VC C =5V) Oscillator period (VC C =3.3V) High time Low time Rise time Fall time Symbol tC LC L tC LC L tC H C X tC LC X tC LC H tC H C L Variable Oscillator (Freq. = 3.5 to 12MHz) Min. 83.3 83.3 20 20 Max. 285.7 1 tC LC L - tC LC X tC LC L - tC H C X 20 20 ns ns ns ns ns Unit
OCT. 2000 Ver 1.2
27
GMS90C320
AC Characteristics for 16MHz version
VCC = 5V: VCC = 3.3V: Variable clock: VC C = 5V + 10%, -15%; VS S = 0V; TA = 0C to 70C (CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF) VC C = 3.3V + 0.3V, -0.6V; VS S = 0V; TA = 0C to 70C (CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF) Vcc = 5V: 1/tC LC L = 3.5 MHz to 16 MHz Vcc = 3.3V: 1/tC LC L = 1 MHz to 16 MHz
External Program Memory Characteristics
16 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN
1)
Variable Oscillator 1/tC LCL = 3.5 to 16MHz Min. 2tC LC L -40 tC LC L -40 tC LC L -40 tC LC L -25 3tC LC L -35 0 tC LC L -8 -10 Max. 4tC LC L -100 3tC LC L -100 tC LC L -20 5tC LC L -115 -
Unit
Max. 150 88 43 198 -
tLH LL tA VLL tLLA X tLLIV tLLP L tP LP H tP LIV tP XIX tP XIZ
1)
85 23 43 38 153 0 55 -10
ns ns ns ns ns ns ns ns ns ns ns ns
tP XA V 1) tA VIV tA ZP L
Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers.
28
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 16MHz External Data Memory Characteristics
16 MHz Oscillator Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tR LR H tW LW H tLLA X 2 tR LD V tR H D X tR H D Z tLLD V tA VD V tLLW L tA VW L tW H LH tQ VW X tQ VW H tW H Q X tR LA Z 275 275 127 0 138 120 28 13 288 23 Max. 183 75 350 398 238 97 0 Variable Oscillator 1/tC LCL = 3.5 to 16MHz Min. 6tC LC L -100 6tC LC L -100 2tC LC L -40 0 3tC LC L -50 4tC LC L -130 tC LC L -35 tC LC L -50 7tC LC L -150 tC LC L -40 Max. 5tC LC L -130 2tC LC L -50 8tC LC L -150 9tC LC L -165 3tC LC L +50 tC LC L +35 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (16MHz) External Clock Drive
Parameter Oscillator period High time Low time Rise time Fall time Symbol tC LC L tC H C X tC LC X tC LC H tC H C L Variable Oscillator (Freq. = 3.5 to 16MHz) Min. 62.5 17 17 Max. 285.7 tC LC L - tC LC X tC LC L - tC H C X 17 17 ns ns ns ns ns Unit
OCT. 2000 Ver 1.2
29
GMS90C320
AC Characteristics for 24MHz version
VCC = 5V: VCC = 3.3V: Variable clock: VC C = 5V + 10%, -15%; VS S = 0V; TA = 0C to 70C (CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF) VC C = 3.3V + 0.3V, -0.6V; VS S = 0V; TA = 0C to 70C (CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF) Vcc = 5V: 1/tC LC L = 3.5 MHz to 24 MHz Vcc = 3.3V: 1/tC LC L = 1 MHz to 24 MHz
External Program Memory Characteristics
24 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN
1)
Variable Oscillator 1/tC LCL = 3.5 to 24MHz Min. 2tC LC L -40 tC LC L -25 tC LC L -25 tC LC L -20 3tC LC L -30 0 tC LC L -5 -10 Max. 4tC LC L -87 3tC LC L -65 tC LC L -10 5tC LC L -60 -
Unit
Max. 80 60 32 148 -
tLH LL tA VLL tLLA X tLLIV tLLP L tP LP H tP LIV tP XIX tP XIZ
1)
43 17 17 22 95 0 37 -10
ns ns ns ns ns ns ns ns ns ns ns ns
tP XA V 1) tA VIV tA ZP L
Interfacing the GMS90C320 to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers.
30
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 24MHz External Data Memory Characteristics
24 MHz Oscillator Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tR LR H tW LW H tLLA X 2 tR LD V tR H D X tR H D Z tLLD V tA VD V tLLW L tA VW L tW H LH tQ VW X tQ VW H tW H Q X tR LA Z 180 180 56 0 75 67 17 5 170 15 Max. 118 63 200 220 175 67 0 Variable Oscillator 1/tC LCL = 3.5 to 24MHz Min. 6tC LC L -70 6tC LC L -70 2tC LC L -27 0 3tC LC L -50 4tC LC L -97 tC LC L -25 tC LC L -37 7tC LC L -122 tC LC L -27 Max. 5tC LC L -90 2tC LC L -20 8tC LC L -133 9tC LC L -155 3tC LC L +50 tC LC L +25 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (24MHz) External Clock Drive
Table 11. Variable Oscillator (Freq. = 3.5 to 24MHz) Min. Oscillator period High time Low time Rise time Fall time tC LC L tC H C X tC LC X tC LC H tC H C L 41.7 12 12 Max. 285.7 tC LC L - tC LC X tC LC L - tC H C X 12 12 ns ns ns ns ns
Parameter
Symbol
Unit
OCT. 2000 Ver 1.2
31
GMS90C320
AC Characteristics for 40MHz version
VC C = 5V + 10%, - 15%; VSS = 0V; TA = 0C to 70C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
External Program Memory Characteristics
40 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN
1)
Variable Oscillator 1/tC LCL = 3.5 to 40MHz Min. 2tC LC L -15 tC LC L -15 tC LC L -15 tC LC L -15 3tC LC L -15 0 tC LC L -5 -5 Max. 4tC LC L -45 3tC LC L -50 tC LC L -10 5tC LC L -60 -
Unit
Max. 55 25 15 65 -
tLH LL tA VLL tLLA X tLLIV tLLP L tP LP H tP LIV tP XIX tP XIZ
1) 1)
35 10 10 10 60 0 20 -5
ns ns ns ns ns ns ns ns ns ns ns ns
tP XA V tA VIV tA ZP L
Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers.
32
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 40MHz External Data Memory Characteristics
at 40 MHz Clock Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tR LR H tW LW H tLLA X 2 tR LD V tR H D X tR H D Z tLLD V tA VD V tLLW L tA VW L tW H LH tQ VW X tQ VW H tW H Q X tR LA Z 120 120 10 0 60 70 10 5 125 5 Max. 75 38 150 150 90 40 0 Variable Clock 1/tC LCL = 3.5 to 40MHz Min. 6tC LC L -30 6tC LC L -30 tC LC L -15 0 3tC LC L -15 4tC LC L -30 tC LC L -15 tC LC L -20 7tC LC L -50 tC LC L -20 Max. 5tC LC L -50 2tC LC L -12 8tC LC L -50 9tC LC L -75 3tC LC L +15 tC LC L +15 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (40MHz) External Clock Drive
Parameter Oscillator period High time Low time Rise time Fall time Symbol tC LC L tC H C X tC LC X tC LC H tC H C L Variable Oscillator (Freq. = 3.5 to 40MHz) Min. 25 10 10 Max. 285.7 tC LC L - tC LC X tC LC L - tC H C X 10 10 ns ns ns ns ns Unit
OCT. 2000 Ver 1.2
33
GMS90C320
AC Characteristics for 50MHz version
VC C = 5V + 10%, - 15%; VSS = 0V; TA = 0C to 70C
(CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF)
Variable Clock : VC C = 5V, 1/ tC LC L = 3.5MHz to 50 MHz
External Program Memory Characteristics
50 MHz Oscillator Parameter Symbol Min. ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN
1)
Variable Oscillator 1/tC LCL = 3.5 to 50MHz Min. 2tC LC L -15 tC LC L -15 tC LC L -15 tC LC L -15 3tC LC L -15 0 tC LC L -5 -5 Max. 4tC LC L -40 3tC LC L -40 tC LC L -10 5tC LC L -55 -
Unit
Max. 40 20 10 45 -
tLH LL tA VLL tLLA X tLLIV tLLP L tP LP H tP LIV tP XIX tP XIZ 1) tP XA V 1) tA VIV tA ZP L
25 5 5 5 45 0 15 -5
ns ns ns ns ns ns ns ns ns ns ns ns
Interfacing the GMS90C320 to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers.
34
OCT. 2000 Ver 1.2
GMS90C320
AC Characteristics for 50MHz External Data Memory Characteristics
at 50 MHz Clock Parameter Symbol Min. RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD high to ALE high Data valid to WR transition Data setup before WR Data hold after WR Address float after RD tR LR H tW LW H tLLA X 2 tR LD V tR H D X tR H D Z tLLD V tA VD V tLLW L tA VW L tW H LH tQ VW X tQ VW H tW H Q X tR LA Z 90 90 25 0 45 50 5 5 100 5 Max. 60 28 120 125 75 35 0 Variable Clock 1/tC LCL = 3.5 to 50MHz Min. 6tC LC L -30 6tC LC L -30 2tC LC L -15 0 3tC LC L -15 4tC LC L -30 tC LC L -15 tC LC L -15 7tC LC L -40 tC LC L -15 Max. 5tC LC L -40 2tC LC L -12 8tC LC L -40 9tC LC L -55 3tC LC L +15 tC LC L +15 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Advance Information (50MHz) External Clock Drive
Parameter Oscillator period High time Low time Rise time Fall time Symbol tC LC L tC H C X tC LC X tC LC H tC H C L Variable Oscillator (Freq. = 3.5 to 50MHz) Min. 20 10 10 Max. 285.7 tC LC L - tC LC X tC LC L - tC H C X 10 10 ns ns ns ns ns Unit
OCT. 2000 Ver 1.2
35
GMS90C320
tLHLL
ALE
tLLPL tAV LL tLLIV tPLIV tPLP H
PSEN
tAZP L tLLAX tP X AV tP X IZ tPX IX INSTR. IN tAV IV A0-A7
PORT 0
A0-A7
PORT 2
A8-A15
A8-A15
Figure 4 External Program Memory Read Cycle
36
OCT. 2000 Ver 1.2
GMS90C320
ALE
tLHLL tW HLH
PSEN
tLLW L
tLLDV tRLR H
RD
tAV LL tLLA X 2 tRLD V tRLA Z tR HDX
DATA IN A0-A7 from PCL INSTR. IN
tRHDZ
PORT 0
A0-A7 from RI or DPL
tA VW L tA V DV
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 5 External Data Memory Read Cycle
ALE
tLHLL tW HLH
PSEN
tLLW L tW LW H
WR
tA VLL tQ V W X tLLA X
A0-A7 from RI or DPL
tW HQ X tQ V W H
DATA OUT A0-A7 from PCL INSTR. IN
PORT 0
tA VW L
PORT 2
P2.0-P2.7 or A8-A15 from DPH
A8-A15 from PCH
Figure 6 External Data Memory Write Cycle
OCT. 2000 Ver 1.2
37
GMS90C320
VC C -0.5V
0.2VCC + 0.9 Test Points
0.45V
0.2VC C - 0.1
AC Inputs during testing are driven at VC C -0.5V for a logic `1' and 0.45V for a logic `0'. Timing measurements are made a VIH m in for a logic `1' and VILm ax for a logic `0'.
Figure 7 AC Testing: Input, Output Waveforms
VLO A D + 0.1 VLO A D VLO A D - 0.1 Timing Reference Points 0.2VCC - 0.1
VO H - 0.1
VO L + 0.1
For timing purposes a port pin is no longer floating when a 100mV change from load voltage occurs and begins to float when a 100mV change from the loaded V O H / VO L level occurs. IO L / IO H 20mA.
Figure 8 Float Waveforms
tCLC L VCC -0.5V 0.7 VCC 0.2 VCC -0.1 0.45V tCLC X tCH CL tCLCH tC HCX
Figure 9 External Clock Cycle
38
OCT. 2000 Ver 1.2
GMS90C320
OSCILLATOR CIRCUIT
CRYSTAL OSCILLATOR MODE
DRIVING FROM EXTERNAL SOURCE
C2 XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14 C1 XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15
N.C.
XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14
External Oscillator Signal
XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15
C1, C2 = 30pF 10pF for Crystals For Ceramic Resonators, contact resonator manufacturer.
Figure 10 Recommended Oscillator Circuits
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
OCT. 2000 Ver 1.2
39
GMS90C320
Plastic Package P-LCC-44
(Plastic Leaded Chip-Carrier)
44PLCC UNIT: INCH
0.695 0.685 0.656 0.650 min. 0.020
0.032 0.026
0.695 0.685
0.656 0.650
0.021 0.013
0.050 BSC
0.012 0.0075
0.120 0.090 0.180 0.165
40
0.630 0.590
OCT. 2000 Ver 1.2
GMS90C320
Plastic Package P-DIP-40 (Plastic Dual in-Line Package)
40DIP
UNIT: INCH
2.075 2.045 0.200 max.
min. 0.015
0.600 BSC 0.550 0.530
0.140 0.120
0.022 0.015
0.065 0.045
0.100 BSC
0-15
0.012 0.008
OCT. 2000 Ver 1.2
41
GMS90C320
Plastic Package P-MQFP-44
(Plastic Metric Quad Flat Package) P-MQFP-44
13.45 12.95 10.10 9.90
UNIT: MM
13.45 12.95
10.10 9.90
2.10 1.95
SEE DETAIL "A" 0.25 0.10
0-7
2.35 max. 0.45 0.30
1.03 0.73 1.60 REF
0.80 BSC
DETAIL "A"
42
OCT. 2000 Ver 1.2
0.23 0.13

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Price & Availability of GMS90C32050

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